Multipldpass Pipelining: Enhancing In-order Microarchitectures to Out-of-order Performance

Out-of-program-order execution has become almost a ubiquitous characteristic of modern processors because of its ability to tolerate variable memory-instruction latency. As designs are becoming increasingly power-conscious, the cost and complexity of the components of out-of-order execution are becoming problematic. Compilers have generally proven adept at planning useful static instruction-level parallelism, but relying solely on the compiler's instruction arrangement has been shown to perform poorly when cache misses occur. This work proposes two multiple-pass pipelining "flea-flicker" microarchitectural techniques , two-pass pipelining and mukipass pipelining, both of which exploit a static compiler's meticulous scheduling as well as advance execution beyond otherwise stalled instructions without the complexity of true out-of-order execution. With twopass pipelining, programs execute on two in-order back-end pipelines coupled by a queue. The "advance" pipeline often defers instructions dispatching with unready operands rather than stalling. The "backup" pipeline allows concurrent resolution of instructions deferred by the first pipeline allowing overlapping of useful "adva,nced" execution with miss resolution. Multipass pipelining is based upon a similar